$_ manjil@4n6:~$

Notiz

Entity Creation and Logic Operators

Entity Creation and Logic Operators
In this task we will be designing digital hardware with the hardware description language VHDL.

Entity Creation and Logical Operators

In this exercise we will be designing digital hardware with the hardware description language VHDL. We will implement full adder. A full adder takes 3 single bit inputs a, b, carry_in and add them to create single bit outputs sum and carry_out

The truth table is given as:

image2

The input and output ports with their widths and types are defined as follows:

image2

We will implement the functionality of a full adder, using full_adder.vhdl file with the given description above.

entity full_adder is
--  Port ( );
Port (
      a_in: in std_ulogic;
      b_in: in std_ulogic;
      carry_in: in std_ulogic;
      sum_out: out std_ulogic;
      carry_out: out std_ulogic
      );
end full_adder;

architecture Behavioral of full_adder is

begin
sum_out <= a_in xor b_in xor carry_in;
carry_out <= (a_in and b_in ) or (a_in and carry_in) or (b_in and carry_in);
end Behavioral;

Understand the notation:

  • => means association or connection. It is commonly used in port map to connect a module’s ports to signals.
  • <= means signal assignment: It assigns a value to a signal.

Schematic view of the output is: image2

Task 2: Run Testbench Given we have a testbench file, full_adder_tb.vhdl.

library ieee;
use ieee.std_logic_1164.all;
use std.env.all;

entity full_adder_tb is
end entity full_adder_tb;

architecture tb of full_adder_tb is 

component full_adder is
    port (
        a_in        : in   std_ulogic;
        b_in        : in   std_ulogic;
        carry_in    : in   std_ulogic;
        sum_out     : out  std_ulogic;
        carry_out   : out  std_ulogic
    );
end component full_adder;

    signal a_sig            : std_ulogic;
    signal b_sig            : std_ulogic;
    signal carry_in_sig     : std_ulogic;
    signal sum_sig          : std_ulogic;
    signal carry_out_sig    : std_ulogic;

begin

    full_adder_dut: full_adder 
        port map (
            a_in        => a_sig,
            b_in        => b_sig,
            carry_in    => carry_in_sig,
            sum_out     => sum_sig,
            carry_out   => carry_out_sig
        );

    fa_test : process
    begin

        a_sig           <= 'X';
        b_sig           <= 'X';
        carry_in_sig    <= 'X';

        wait for 100 ns;

        a_sig           <= '0';
        b_sig           <= '0';
        carry_in_sig    <= '0';

        wait for 20 ns;
        
        assert sum_sig = '0'        report "Test Failure: sum output wrong! expected value '0'"       severity failure;
        assert carry_out_sig = '0'  report "Test Failure: carry output wrong! expected value '0'"     severity failure;

        a_sig           <= '1';
        b_sig           <= '0';
        carry_in_sig    <= '0';

        wait for 20 ns;

        assert sum_sig = '1'        report "Test Failure: sum output wrong! expected value '1'"      severity failure;
        assert carry_out_sig = '0'  report "Test Failure: carry output wrong! expected value '0'"    severity failure;

        a_sig           <= '0';
        b_sig           <= '1';
        carry_in_sig    <= '0';

        wait for 20 ns;

        assert sum_sig = '1'        report "Test Failure: sum output wrong! expected value '1'"      severity failure;
        assert carry_out_sig = '0'  report "Test Failure: carry output wrong! expected value '0'"    severity failure;

        a_sig           <= '1';
        b_sig           <= '1';
        carry_in_sig    <= '0';

        wait for 20 ns;

        assert sum_sig = '0'        report "Test Failure: sum output wrong! expected value '0'"      severity failure;
        assert carry_out_sig = '1'  report "Test Failure: carry output wrong! expected value '1'"    severity failure;

        a_sig           <= '0';
        b_sig           <= '0';
        carry_in_sig    <= '1';

        wait for 20 ns;

        assert sum_sig = '1'        report "Test Failure: sum output wrong! expected value '1'"      severity failure;
        assert carry_out_sig = '0'  report "Test Failure: carry output wrong! expected value '0'"    severity failure;
        
        a_sig           <= '1';
        b_sig           <= '0';
        carry_in_sig    <= '1';

        wait for 20 ns;

        assert sum_sig = '0'        report "Test Failure: sum output wrong! expected value '0'"      severity failure;
        assert carry_out_sig = '1'  report "Test Failure: carry output wrong! expected value '1'"    severity failure;

        a_sig           <= '0';
        b_sig           <= '1';
        carry_in_sig    <= '1';

        wait for 20 ns;

        assert sum_sig = '0'        report "Test Failure: sum output wrong! expected value '0'"      severity failure;
        assert carry_out_sig = '1'  report "Test Failure: carry output wrong! expected value '1'"    severity failure;

        a_sig           <= '1';
        b_sig           <= '1';
        carry_in_sig    <= '1';

        wait for 20 ns;

        assert sum_sig = '1'        report "Test Failure: sum output wrong! expected value '1'"      severity failure;
        assert carry_out_sig = '1'  report "Test Failure: carry output wrong! expected value '1'"    severity failure;

        a_sig           <= 'X';
        b_sig           <= 'X';
        carry_in_sig    <= 'X';

        wait for 100 ns;
        
        report "Test: Full Adder test passed!";
        std.env.finish;
               
    end process fa_test;

end architecture tb;

Our testbench passed: image2

Compared with the design, the testbench entity has no ports. Its architecture additionally contains an instance of the design under test, internal connecting signals, input stimuli, simulation delays, assertions to check the outputs, and a command to end the simulation.

Investigate. Decode. Educate